18.5.2 DWDT Watchdog 1 Mode Register

Write access to this register has no effect if the LOCKMR command is issued in WDT1_CR (unlocked on hardware reset).

The WDT1_MR register values must not be modified within three MD_SLCK periods following a restart of the watchdog performed by a write access in WDT1_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.

Name: WDT1_MR
Offset: 0x0004
Reset: 0x00000030
Property: Read/Write

Bit 3130292827262524 
  WDDBG1HLTWDDBG0HLTWDIDLEHLT     
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    WDDIS  WDNRSTDIS  
Access R/WR/W 
Reset 00 
Bit 76543210 
   RPTHRSTPERIODRST     
Access R/WR/W 
Reset 11 

Bit 30 – WDDBG1HLT Watchdog Core 1 Debug Halt

ValueDescription
0

The Watchdog 1 runs when the coprocessor is in Debug state.
1

The Watchdog 1 stops when the coprocessor is in Debug state.

Bit 29 – WDDBG0HLT Watchdog Core 0 Debug Halt

ValueDescription
0

The Watchdog 1 runs when the processor is in Debug state.
1

The Watchdog 1 stops when the processor is in Debug state.

Bit 28 – WDIDLEHLT Watchdog Idle Halt

ValueDescription
0

The watchdog runs when the system is in Idle state.
1

The watchdog stops when the system is in Idle state.

Bit 12 – WDDIS Watchdog Disable

ValueDescription
0

Enables the Watchdog Timer.
1

Disables the Watchdog Timer.

Bit 9 – WDNRSTDIS Watchdog Reset NRST Pin Disable

ValueDescription
0

A watchdog reset asserts the NRST pin.
1

A watchdog reset does not assert the NRST pin.

Bit 5 – RPTHRST Repeat Threshold Reset Enable

ValueDescription
0

No reset is generated if the watchdog is restarted before the RPTH threshold (early restart).
1

A reset is generated if the watchdog is restarted before the RPTH threshold.

Bit 4 – PERIODRST Watchdog Overflow Period Reset Enable

ValueDescription
0

No reset is generated if the watchdog reaches 0.
1

A reset is generated once the watchdog reaches 0.