18.5.18 DWDT Watchdog 0 Interrupt Mask Register
| Name: | WDT0_IMR |
| Offset: | 0x1230 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RLDERR | W1RPTHINT | W1PERINT | LVLINT | RPTHINT | PERINT | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – RLDERR Reload Command Error Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt on Watchdog 0 attempt to reload with an incorrect key (WDT0_CR.KEY) is disabled. |
| 1 | The interrupt on Watchdog 0 attempt to reload with an incorrect key (WDT0_CR.KEY) is enabled. |
Bit 4 – W1RPTHINT Watchdog 1 Repeat Threshold Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt is disabled when Watchdog 1 is reloaded before the period configured in WDT1_WL.RPTH. |
| 1 | The interrupt is enabled when Watchdog 1 is reloaded before the period configured in WDT1_WL.RPTH. |
Bit 3 – W1PERINT Watchdog 1 Overflow Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt is disabled when Watchdog 1 overflow occurs. |
| 1 | The interrupt is enabled when Watchdog 1 overflow occurs. |
Bit 2 – LVLINT Interrupt Level Threshold Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt is disabled when the Watchdog 0 counter reaches the period defined in WDT0_IL.LVLTH. |
| 1 | The interrupt is enabled when the Watchdog 0 counter reaches the period defined in WDT0_IL.LVLTH. |
Bit 1 – RPTHINT Reload Repeat Period Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt is disabled when the Watchdog 0 is reloaded before the period configured in WDT0_WL.RPTH. |
| 1 | The interrupt is enabled when the Watchdog 0 is reloaded before the period configured in WDT0_WL.RPTH. |
Bit 0 – PERINT Overflow Period Interrupt Mask
| Value | Description |
|---|---|
| 0 | The interrupt is disabled when Watchdog 0 overflow occurs. |
| 1 | The interrupt is enabled when Watchdog 0 overflow occurs. |