2.4.2 Clocking Structure

Both the DDR subsystem and the DDR PHY-only solution require a dedicated PLL to generate the clocks, which are then distributed throughout the subsystem using HS_IO_CLK routes, dedicated pads, and fabric clock routing. This PLL generates aligned clocks for all sub-blocks for smooth operation and synchronous communication with the user logic.

The PLL generates the following required clocks:

• REF_CLK— This clock is routed to the PHY for clocking the DDR memory device.
• HS_IO_CLK— This clock routed to I/O lanes and the training logic.
• HS_IO_CLK_270— HS_IO_CLK phase shifted by 270. This clock is also routed to I/O lanes and the training logic.
• SYS_CLK— This clock is routed to the DDR controller, training logic, and user logic in the fabric.

The HS_IO_CLK and REF_CLK clocks are generated with the same frequency and phase. The REF_CLK to SYS_CLK ratio is 4:1.

The following illustration shows the clocking structure of the DDR subsystem.