2.4.1.7 ECC

When ECC is enabled, the DDR controller computes an 8-bit ECC for every 64-bit data to support SECDED. A write operation computes and stores ECC along with the data, and a read operation reads and checks the data against the stored ECC. Therefore, when ECC is enabled, single or double-bit errors might be received when reading uninitialized memory locations. To prevent this, all memory locations must be written to before being read.

For a non 64-bit write operation, the DDR controller performs a read-modify-write (RMW) operation as follows:

• Reads the data from DDR memory (4 or 8 DDR memory bursts)
• Modifies the read data with the user data
• Computes the ECC and writes to DDR memory

The DDR subsystem uses status signals to indicate a single-bit error (ECC_ERROR_1BIT) or a double-bit error (ECC_ERROR_2BIT) along with the error position (ECC_ERROR_POS) to the fabric. The following table lists the mapping of the ECC_ERROR_POS bits to the error bit position.