2.4.1 DDR Controller
(Ask a Question)The Fabric DDR controller is a soft IP core that consists of the following blocks:
- Control and timing block—contains the main controller logic.
- Initialization control block—performs the initialization sequence after system reset (RESET_N) is deactivated or when dynamic reinitialization control (CTRLR_INIT) is pulsed.
- Bank management block—keeps track of the last opened row and bank to minimize command overhead.
- Refresh/ZQ calibration control block—performs automatic refresh/ZQ calibration commands to maintain data integrity.
- Queue control block—allows new requests to be accepted on every clock cycle as long as the queue is not full.
- Data control block—handles multiplexing and de-multiplexing of data flowing to and from the DDR SDRAM devices.
- Multi-burst block—allows requests longer than the programmed memory burst length. Also handles requests with starting addresses not aligned on a burst boundary, breaking the requests up as necessary to prevent data wrapping.
The queue-based implementation enables the Fabric DDR controller to optimize throughput and efficiency by looking ahead into the queue to perform precharges before the read and write commands are issued. Configure the queue depth to 3 or 4 using the Command queue depth option on DDR Configurator > Controller tab. For DDR4/LPDDR3, the default queue depth is 3.
The core also supports SECDED ECC for 40-bit and 72-bit data buses. SECDED ECC detects and corrects single-bit errors, and detects but does not correct double-bit errors. It cannot detect more than two bit errors in the data bus.
The following figure shows the functional blocks of the Fabric DDR controller.
The following sections describe the key functions of the DDR controller.