2.6.1.1.1 Sample Write Sequence

The following figure shows a sample write sequence consisting of single write request.

The following points summarize a write sequence:

1. The L_W_REQ signal is first asserted along with the L_ADDR signal, and the L_B_SIZE signal is set to 128.
2. If the L_BUSY signal is not asserted in clock cycle 1 (indicating that the request is accepted by the subsystem), the L_W_REQ signal remains asserted. The L_ADDR and L_B_SIZE signals are updated for the next write request.
3. The L_W_REQ signal is deasserted, indicating that no other write requests are required.
4. As a result of the write request, the subsystem asserts the row address (A), bank address (BA), and chip select (CS_N) using the activate command to open the bank at the requested row.
5. As a result of the write request, the subsystem issues a write command with the appropriate column address.In response to the next write request, the subsystem issues another write command with the corresponding column address.
6. The subsystem requests data in the native interface by asserting the L_D_REQ signal.

In this sequence, all the writes are to the same bank and row. If the next write request targets a different bank, the DDR subsystem may have to issue a precharge and/or activate commands prior to issuing write commands.