5.5.3.1 Timing Constraints

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The HS_IO_CLK, HS_IO_CLK_90, and SYS_CLK Clocks generated using the dedicated PLL requires timing constraints for synthesis, place and route, and timing verification. To generate these timing constraints, select the Timing tab in Constraint Manager, and click Derive Constraints, as shown in the following figure. It also generates the required multi cycle/false path constraints.

Figure 5-15. Constraint Manager-Derive Constraints Tab

When prompted, Click Yes to apply the derived constraints for synthesis, place and route, and timing verification.

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