5.6.3 RTL_Fast Simulation
(Ask a Question)RTL_fast simulation is same as RTL_full simulation except that QDR subsystem loads the training delays as per selected configuration and skips the training sequence to assert the TRAINING_COMPLETE signal.
In the following example, a design is created to access the QDR memory with 18-bit data width, 22-bit address width, and burst size of 4.
Note: The waveform output of the QDR RTL-Fast simulation will be provided in the next revision
of this document.