2.4.3.2 Training Logic for Fabric DDR Controller

The training logic manages the DFI 4.0 training requests between the integrated PHY and DDR controller modules, and performs the following operations.

• Clock training
• Write leveling
• Read leveling
• I/O calibration

For more information, see Training Logic.

For information about initialization sequence of DDR3, DDR4, and LPDDR3, see Initialization Sequence.