5.4.1 Write Strobe Mapping

Mapping of the write strobe signal WSTRB to write data WDATA is done on a phased basis, by mapping WDATA to the QDR data bus D, as shown in Figure 5-10 and Figure 5-11. However, it is also aligned to BWSx_N signals on the QDR interface as follows. Note that the following example is for SRAM_DWIDTH of 36, or x36 mode.

Table 5-4. WSTRB to BWS Mapping
WSTRB IndexBWS Index
7:00
15:81
23:162
31:243

Within each WSTRB byte, each bit corresponds to a clock cycle (phase) and either rising or falling edge. A complete mapping for write data bus WDATA to WSTRB is listed in the following tables, for x36, x18, and x9 modes.

Table 5-5. Write Data to Write Strobe Mapping (x36)
WSTRB_MAPPING_INDEXWDATA INDEXRISING/FALLINGCLOCK CYCLE
0012345678RISING1
8363738394041424344FALLING1
16727374757677787980RISING2
24108109110111112113114115116FALLING2
1144145146147148149150151152RISING3
9180181182183184185186187188FALLING3
17216217218219220221222223224RISING4
25252253254255256257258259260FALLING4
291011121314151617RISING1
10454647484950515253FALLING1
18818283848586878889RISING2
26117118119120121122123124125FALLING2
3153154155156157158159160161RISING3
11189190191192193194195196197FALLING3
19225226227228229230231232233RISING4
27261262263264265266267268269FALLING4
4181920212223242526RISING1
12545556575859606162FALLING1
20909192939495969798RISING2
28126127128129130131132133134FALLING2
5162163164165166167168169170RISING3
13198199200201202203204205206FALLING3
21234235236237238239240241242RISING4
29270271272273274275276277278FALLING4
6272829303132333435RISING1
14636465666768697071FALLING1
2299100101102103104105106107RISING2
30135136137138139140141142143FALLING2
7171172173174175176177178179RISING3
15207208209210211212213214215FALLING3
23243244245246247248249250251RISING4
31279280281282283284285286287FALLING4
(1) The mapping is not sequential. First bit of write_strobe corresponds to the first 9 wdata bits. The second bit does not correspond to the next 9 wdata bits.
Table 5-6. Write Data to Write Strobe Mapping (x18)
WSTRB_MAPPING_INDEXWDATA INDEXRISING/FALLINGCLOCK CYCLE
0012345678RISING1
8363738394041424344FALLING1
1727374757677787980RISING2
9108109110111112113114115116FALLING2
291011121314151617RISING3
10454647484950515253FALLING3
3818283848586878889RISING4
11117118119120121122123124125FALLING4
4181920212223242526RISING1
12545556575859606162FALLING1
5909192939495969798RISING2
13126127128129130131132133134FALLING2
6272829303132333435RISING3
14636465666768697071FALLING3
799100101102103104105106107RISING4
15135136137138139140141142143FALLING4
(1) The mapping is not sequential. First bit of write_strobe corresponds to the first 9 wdata bits. The second bit does not correspond to the next 9 wdata bits.
Table 5-7. Write Data to Write Strobe Mapping (x9)
WSTRB_MAPPING_INDEXWDATA INDEXRISING/FALLINGCLOCK CYCLE
0012345678RISING1
1363738394041424344FALLING2
291011121314151617RISING3
3454647484950515253FALLING4
4181920212223242526RISING1
5545556575859606162FALLING2
6272829303132333435RISING3
7636465666768697071FALLING4