5.4.1.2 Burst of 4

In the burst of 4 mode (SRAM_BURST = 0), only half the WADDR/RADDR and WRITE_N/READ_N are utilized, because each SYS_CLK cycle transaction corresponds to only 2 (instead of 4) K clock transactions. A sample write transaction in burst of 4 mode with SRAM_AWIDTH=20 and SRAM_DWIDTH=36 is show in the following figure.

In burst of 4 mode, 2 write transactions (WRITE_N[0,1]) are completed in one SYS_CLK cycle. In each transaction data is 36-bit wide and address is 20-bit wide. The 4 write transactions must be triggered with respect to KP clock, which is derived from SYS_CLK internally. The first write (when WRITE_N[0] = 0) occurs at the first falling edge of the WPS_N write enable signal. The second write (when WRITE_N[1] = 0) occurs at the next falling edge of WPS_N.

Write transaction is performed as follows:

• When the WPS_N enable signal is '0', 2 36-bit data are written in the specified address 'A' in a single system clock.
• A1= WADDR[19:0], A2= WADDR[39:20].
• During each write enable, 4 write transactions are performed in each burst, as follows:
  • A1 address D0=WDATA[35:0], D1=WDATA[71:36], D2=WDATA[107:72] and D3=WDATA[143:108].
  • A2, D4=WDATA[179:144] and D5=WDATA[215:180], D6=WDATA[251:216] and D7=WDATA[287:252]