5.4.1.1 Burst of 2

In burst of 2 mode (SRAM_BURST=1), all bits of both WADDR/RADDR and WRITE_N/READ_N (the corresponding control signals) are used. A sample write transfer with SRAM_DWIDTH=18 and SRAM_AWIDTH=20 is shown in the following figure.

In burst of 2 mode, 4 write transactions (WRITE_N[0,1,2,3]) are completed in one SYS_CLK cycle. In each transaction data is 18-bit wide and address is 20-bit wide. The 4 write transactions must be triggered with respect to KP clock, which is derived from SYS_CLK internally. The first write (when WRITE_N[0] = 0) occurs at the first falling edge of the WPS_N write enable signal. The second write (when WRITE_N[1] = 0) occurs at the next falling edge of WPS_N. Similarly, the remaining writes are triggered.

Write transaction is performed as follows:

• When the WPS_N enable signal is '0', four 18-bit data are written in the specified address 'A' in a single system clock.
• A1= WADDR[19:0], A2= WADDR[39:20], A3= WADDR[59:40], A4= WADDR[79:60]
• During each write enable (WPS_N), 2 write transactions are performed as follows:
  • A1 address D0 = WDATA[17:0] and D1=WDATA[35:18]
  • A2, D2 = WDATA[53:36] and D3=WDATA[71:54]
  • A3, D4 = WDATA[89:72] and D5=WDATA[107:90]
  • A4, D6 = WDATA[125:108] and D7=WDATA[143:126]

Read transactions are not shown, but are similar, as each RPS_N assertion and the corresponding A bus values are derived from the four slices of READ_N and RADDR, respectively.