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ATWINC15x0B-MU IEEE® 802.11 b/g/n Network Controller SoC
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Introduction
Features
1
Ordering Information and IC Marking
2
Functional Overview
2.1
Block Diagram
2.2
Pinout Information
2.3
Pinout Description
2.4
Package Description
3
Clocking
3.1
Crystal Oscillator
3.2
Low-Power Oscillator
4
CPU and Memory Subsystem
4.1
Processor
4.2
Memory Subsystem
4.3
Nonvolatile Memory (eFuse)
5
WLAN Subsystem
5.1
MAC
5.2
PHY
5.3
Radio
6
External Interfaces
6.1
Interfacing with the Host Microcontroller
6.2
SPI Slave Interface
6.3
UART Interface
6.4
GPIO Pins
7
Power Management
7.1
Power Architecture
7.2
Power Consumption
7.3
Power Up/Power Down Sequence
7.4
Digital I/O Pin Behavior During Power-Up Sequences
7.5
Chip Reset
8
Electrical Specifications
8.1
Absolute Maximum Ratings
8.2
Recommended Operating Conditions
8.3
DC Electrical Characteristics
8.4
Current Consumption in Various Device States
8.5
Wi-Fi Performance Characteristics
9
Reference Design
9.1
Bill of Material
10
Design Consideration
10.1
Placement and Routing Guidelines
10.2
Sensitive Traces
10.3
Interferers
10.4
Antenna
10.5
Reflow Profile Information
11
Package Outline Drawing
12
Reference Documentation
13
Document Revision History
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