SPI Slave Interface

The ATWINC15x0B provides a Serial Peripheral Interface (SPI) that operates as an SPI slave. This is the main interface to the host. The SPI slave interface can be used to control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in the following table. The RXD pin is the same as the Master Output, Slave Input (MOSI) and the TXD pin is the same as the Master Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is available following Reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO.

Table 1. ATWINC15x0B SPI Slave Interface Pin Mapping
Pin Number Pin Name SPI Function
9 SDIO_SPI_CFG Must be tied to VDDIO
16 SSN Active low slave select
18 SPI_SCK Serial clock
13 SPI_RXD Serial data receive (MOSI)
17 SPI_TXD Serial data transmit (MISO)

When the SPI is not selected, that is, when SSN is high, the SPI interface does not interfere with data transfers between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line.

The SPI slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiates DMA transfer.

The SPI slave interface supports four Standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.

Table 2. SPI Modes
0(1) 0 0
1 0 1
2 1 0
3 1 1
  1. 1. The ATWINC15x0 firmware uses SPI MODE 0 to communicate with the host.
Figure 1. ATWINC15x0B SPI Slave Clock Polarity and Clock Phase Timing

The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.

Figure 2. ATWINC15x0BSPI Slave Timing Diagram
Table 3. ATWINC15x0B SPI Slave Timing Parameters (1)
Parameter Symbol Min. Max. Units
Clock input frequency(2) fSCK 48 MHz
Clock low pulse width tWL 4 ns
Clock high pulse width tWH 5
Clock rise time tLH 0 7
Clock fall time tHL 0 7
TXD output delay(3) tODLY 4 9 from SCK fall
RXD input setup time tISU 1
RXD input hold time tIHD 5
SSN input setup time tSUSSN 3
SSN input hold time tHDSSN 5.5
  1. 1.Timing is applicable to all the SPI modes.
  2. 2.Maximum clock frequency specified is limited by the SPI slave interface internal design. Actual maximum clock frequency can be lower and depends on the specific PCB layout.
  3. 3.Timing is based on 15 pF output loading. Under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/fSCK.