65.14.55 SDMMC Retuning Interrupt Signal Enable Register
| Name: | SDMMC_RTISIER |
| Offset: | 0x219 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEVT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – TEVT Retuning Timer Event
0 (MASKED): No interrupt is generated when the TEVT status rises in SDMMC_RTISTR.
1 (ENABLED): An interrupt is generated when the TEVT status rises in SDMMC_RTISTR.