65.14.59 SDMMC Capabilities Control Register
| Name: | SDMMC_CACR |
| Offset: | 0x230 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| KEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CAPWREN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 15:8 – KEY[7:0] Key
| Value | Name | Description |
|---|---|---|
| 0x46 | KEY | Writing any other value in this field aborts the write operation of the CAPWREN bit. Always reads as 0. |
Bit 0 – CAPWREN Capabilities Write Enable
This bit can only be written if the value of KEY corresponds to 0x46.
| Value | Description |
|---|---|
| 0 | Capabilities registers (SDMMC_CA0R, SDMMC_CA1R and SDMMC_CA1R) cannot be written. |
| 1 | Capabilities registers (SDMMC_CA0R, SDMMC_CA1R and SDMMC_CA1R) can be written. |