65.14.47 SDMMC e.MMC Control 3 Register
| Name: | SDMMC_MC3R |
| Offset: | 0x206 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DQSUPVAL[2:0] | ESMEN | HS400EN | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 5:3 – DQSUPVAL[2:0] DQS Delay Update Timer Value
0: DQS delay update is performed each time a command is sent to the device.
n: DQS delay update is performed before sending the command only if a timer delay is elapsed. The timer delay t is defined as follows:
Bit 1 – ESMEN Enhanced Strobe Mode Enable
This field is used to enable the Enhanced Strobe Mode. User must ensure that this mode is supported by the e.MMC device (Only devices compliant with the Embedded Multimedia Card (e.MMC) Electrical Standard 5.1 and further support this mode).
0 (DISABLED): Enhanced Strobe mode is disabled.
1 (ENABLED): Enhanced Strobe mode is enabled.
Bit 0 – HS400EN HS400 Mode Enable
This field is used to select the e.MMC HS400 mode.
0 (DISABLED): HS400 mode is disabled.
1 (ENABLED): HS400 mode is enabled.
If Preset Value Enable is set to 1, SDMMC sets SDCLK Frequency Select (SDCLKFSEL), Clock Generator Select (CLKGSEL) in SDMMC_CCR and Driver Strength Select (DRVSEL) according to SDMMC_PVR. In this case, SDMMC_EPVR8 register is selected by this bit. The user needs to reset SD Clock Enable (SDCLKEN) before changing this field to avoid generating a clock glitch. After setting this field, the user sets SDCLKEN to 1 again.