65.14.35 SDMMC Capabilities 1 Register

Note: The reset values match the capabilities of the MPU alone. The user should adjust the capability registers so that they also match the board design. Modify preset values only if the Capabilities Write Enable (CAPWREN) bit is set to 1 in SDMMC_CACR.

Name:	SDMMC_CA1R
Offset:	0x44
Reset:	0x00010F77
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	CLKMULT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	1


Bit	15	14	13	12	11	10	9	8
	RTMOD[1:0]		TSDR50		TCNTRT[3:0]
Access	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Reset	0	0	0		1	1	1	1


Bit	7	6	5	4	3	2	1	0
		DRVDSUP	DRVCSUP	DRVASUP		DDR50SUP	SDR104SUP	SDR50SUP
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		1	1	1		1	1	1

Bits 23:16 – CLKMULT[7:0] Clock Multiplier

This field indicates the multiplier factor between the Base Clock (BASECLK) used for the Divided Clock Mode and the Multiplied Clock (MULTCLK) used for the Programmable Clock mode (see SDMMC_CCR).

Reading this field to 0 means that the Programmable Clock mode is not supported.

f_{MULTCLK} = f_{BASECLK} \times (CLKMULT + 1)

Bits 15:14 – RTMOD[1:0] Retuning Modes

This field selects the retuning method and limits the maximum data length.

There are two retuning timings: Retuning Request (RTREQ) controlled by the SDMMC, and expiration of a Retuning timer controlled by the user. By receiving either timing, the user executes the retuning procedure just before a next command issue.

The maximum data length per read/write command is restricted so that retuning procedures can be inserted during data transfers.

Retuning Mode 1:

The SDMMC does not have any internal logic to detect when retuning needs to be performed. In this case, the user should maintain all retuning timings by using the Retuning Timer. To enable inserting the retuning procedure during data transfers, the data length per Read/Write command must be limited to 4 Mbytes.

Retuning Mode 2:

The SDMMC has the capability to indicate the retuning timing by Retuning Request (RTREQ) during data transfers. Then the data length per Read/Write command must be limited to 4 Mbytes.

During nondata transfer, retuning timing is determined by either Retuning Request or Retuning Timer. If Retuning Request is used, Retuning Timer should be disabled.

Retuning Mode 3:

The SDMMC has the capability to take care of the retuning during data transfer (Auto Retuning). Retuning Request is not generated during data transfers and there is no limitation to data length per Read/Write command.

During nondata transfer, retuning timing is determined either by Retuning Request or Retuning Timer. If Retuning Request is used, Retuning Timer should be disabled.


Value	Name	Description	Data Length
0	MODE1	Timer	4 Mbytes (Max)
1	MODE2	Timer and Retuning Request	4 Mbytes (Max)
2	MODE3	Auto Retuning (for transfer) Timer and Retuning Request	Any
3	–	Reserved	–

Bit 13 – TSDR50 Use Tuning for SDR50

If this bit is set to 1, the SDMMC requires tuning to operate SDR50 (tuning is always required to operate SDR104).

Value	Description
0	SDR50 does not require tuning.
1	SDR50 requires tuning.

Bits 11:8 – TCNTRT[3:0] Timer Count For Retuning

This field indicates an initial value of the Retuning Timer for Retuning Mode (RTMOD) 1 to 3. Reading this field at 0 means that the Retuning Timer is disabled. The Retuning Timer initial value ranges from 0 to 1024 seconds.

t_TIMER = 2^{(TCNTRT
– 1)}Seconds

Bit 6 – DRVDSUP Driver Type D Support

Value	Description
0	Driver type D is not supported.
1	Driver type D is supported.

Bit 5 – DRVCSUP Driver Type C Support

Value	Description
0	Driver type C is not supported.
1	Driver type C is supported.

Bit 4 – DRVASUP Driver Type A Support

Value	Description
0	Driver type A is not supported.
1	Driver type A is supported.

Bit 2 – DDR50SUP DDR50 Support

Value	Description
0	DDR50 mode is not supported.
1	DDR50 mode is supported.

Bit 1 – SDR104SUP SDR104 Support

Value	Description
0	SDR104 mode is not supported.
1	SDR104 mode is supported.

Bit 0 – SDR50SUP SDR50 Support

Value	Description
0	SDR50 mode is not supported.
1	SDR50 mode is supported.