65.14.49 SDMMC AHB Control Register
| Name: | SDMMC_ACR |
| Offset: | 0x208 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFQOS[3:0] | BUFM[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BMAX[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 15:12 – DFQOS[3:0] Descriptor Fetch QOS
This field defines the QOS value of ADMA AHB access when fetching descriptor. For all other accesses, the QOS is set to 0.
Bits 9:8 – BUFM[1:0] AHB Bufferable Mode
This field defines if last access of data transfer is bufferable or not.
| Value | Name | Description |
|---|---|---|
| 0 | NEVER |
All SDMA/ADMA AHB accesses are not bufferable. |
| 1 | ALWAYS |
All SDMA/ADMA AHB accesses are bufferable. |
| 2 | BLOCK |
All SDMA/ADMA AHB accesses are bufferable except the last access of a data block. |
| 3 | TRANSFER |
All SDMA/ADMA AHB accesses are bufferable except the last access of a data transfer. |
Bits 1:0 – BMAX[1:0] AHB Maximum Burst
This field selects the maximum burst size in case of DMA transfer.
| Value | Name | Description |
|---|---|---|
| 0 | INCR16 | The maximum burst size is INCR16. |
| 1 | INCR8 | The maximum burst size is INCR8. |
| 2 | INCR4 | The maximum burst size is INCR4. |
| 3 | SINGLE | Only SINGLE transfers are performed. |