65.14.61 SDMMC Calibration Control Register
| Name: | SDMMC_CALCR |
| Offset: | 0x240 |
| Reset: | 0x0000500E |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CALPBP[3:0] | CALP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CALNBP[3:0] | CALN[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CNTVAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BPEN | TUNDIS | ALWYSON | CLKDIV[2:0] | EN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 0 | ||
Bits 31:28 – CALPBP[3:0] Calibration P Bypass Value
Calibration code applied for the p-channel transistors when BPEN is set to 1. This field is ignored if BPEN is 0.
Bits 27:24 – CALP[3:0] Calibration P Status
Calibration code for the p-channel transistors to match the required output impedance.
Bits 23:20 – CALNBP[3:0] Calibration N Bypass Value
Calibration code applied for the n-channel transistors when BPEN is set to 1. This field is ignored if BPEN is 0.
Bits 19:16 – CALN[3:0] Calibration N Status
Calibration code for the n-channel transistors to match the required output impedance.
Bits 15:8 – CNTVAL[7:0] Calibration Counter Value
Defines the number of XXXX cycles (divided by 4) required to cover the I/O calibration cell startup time.
tSTARTUP = 2 μs
Bit 6 – BPEN Calibration Bypass Enabled
| Value | Description |
|---|---|
| 0 |
Calibration bypass is not enabled. |
| 1 |
Calibration bypass is enabled. CALPBP and CALNBP codes are applied to the calibration cell. |
Bit 5 – TUNDIS Calibration During Tuning Disabled
| Value | Description |
|---|---|
| 0 |
Calibration is launched before each tuning. |
| 1 | Calibration is not launched at tuning. |
Bit 4 – ALWYSON Calibration Analog Always ON
| Value | Description |
|---|---|
| 0 |
Calibration analog is shut down after each calibration. |
| 1 |
Calibration analog remains powered after calibration. |
Bits 3:1 – CLKDIV[2:0] Calibration Clock Division
The clock applied to the calibration cell is divided by CLKDIV + 1
Bit 0 – EN PADs Calibration Enable
| Value | Description |
|---|---|
| 0 |
SDMMC I/O calibration disabled. |
| 1 | SDMMC I/O calibration enabled. |