65.14.62 SDMMC Extended Preset Value Register 8
The Preset Value register 8 is effective based on the selected bus speed mode. The table below defines the conditions to select SDMMC_EPVR8.
| Selected Bus Speed Mode | HS400EN (SDMMC_MC3R) |
|---|---|
| HS400 | 1 |
When Preset Value Enable (PVALEN) in SDMMC_HC2R is set to 1, SDCLK Frequency Select (SDLCKFSEL) and Clock Generator Select (CLKGSEL) in SDMMC_CCR, and Driver Strength Select (DRVSEL) in SDMMC_HC2R are automatically set based on the selected bus speed mode. This means that the user does not need to set these fields when preset is enabled. Before starting the initialization sequence, the user needs to set a clock preset value to SDMMC_CCR.SDCLKFSEL. Bit PVALEN can be set to 1 after the initialization is completed.
| Name: | SDMMC_EPVR8 |
| Offset: | 0x244 |
| Reset: | 0x0000 |
| Property: | Read/Write |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DRVSEL[1:0] | CLKGSEL | SDCLKFSEL[9:8] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SDCLKFSEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:14 – DRVSEL[1:0] Driver Strength Select
See DRVSEL in SDMMC_HC2R.
Bit 10 – CLKGSEL Clock Generator Select
See CLKGSEL in SDMMC_CCR.
Bits 9:0 – SDCLKFSEL[9:0] SDCLK Frequency Select
See SDCLKFSEL in SDMMC_CCR.