65.14.54 SDMMC Retuning Interrupt Status Enable Register
| Name: | SDMMC_RTISTER |
| Offset: | 0x218 |
| Reset: | 0x00 |
| Property: | Read/Write |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEVT | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – TEVT Retuning Timer Event
0 (MASKED): The TEVT status flag in SDMMC_RTISTR is masked.
1 (ENABLED): The TEVT status flag in SDMMC_RTISTR is enabled.