60.7.20 SECUMOD Normal Interrupt Mask Protection Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
Note: Register reset value is 0x00000000 after peripheral reset. Other reset values are
defined after backup reset.
| Name: | SECUMOD_NIMPR |
| Offset: | 0x0094 |
| Reset: | see Note |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DET3 | DET2 | DET1 | DET0 | ||||||
| Access | R | R | R | R | |||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VDDCPUH | VDDCOREH | VDDCPUL | VDDCOREL | VBATH | VBATL | ||||
| Access | R | R | R | R | R | R | |||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TPMH | TPML | MBZ | REGANA | JTAG | TST | DBLFM | DWDT_SW | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset |