60.7.12 SECUMOD Dynamic Signatures Tuning Register
Name: | SECUMOD_DYSTUNE |
Offset: | 0x0074 |
Reset: | 0x00010501 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PERIOD[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PERIOD[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
RX_OK_CORREL_NUMBER[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NOPA | RX_ERROR_THRESHOLD[6:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Bits 31:16 – PERIOD[15:0] Signature Clock Period
This 32-bit field contains the dividing ratio applied on ICLK to build the signature clock:
tSIGCLK =(8*PERIOD) * tICLK.
Writing 0 has no effect: 1 ≤ PERIOD ≤ 65535
Bits 15:8 – RX_OK_CORREL_NUMBER[7:0] Error Counter Reset Threshold
This 16-bit field contains the number of consecutive matching patterns which must be received to consider that the external signature carrier is safe (again), and to forget any ongoing dynamic intrusion.
Writing values lower than 0x5 has no effect: 5 ≤ RX_OK_CORREL_NUMBER ≤ 255
Bit 7 – NOPA No Periodic Alarm
Value | Description |
---|---|
0 | The alarm is regenerated periodically while intrusion is maintained. |
1 | The alarm is not regenerated periodically while intrusion is maintained. |
Bits 6:0 – RX_ERROR_THRESHOLD[6:0] Error Detection Threshold
This 7-bit field contains the number of mismatching patterns which must be received to trigger an alarm.
Writing 0 has no effect: 1 ≤ RX_ERROR_THRESHOLD ≤ 127