60.7.22 SECUMOD General Purpose Security Bits Register
This register enables the control of environmental sensors or security mechanisms linked to the SECUMOD.
| Name: | SECUMOD_GPSBR |
| Offset: | 0x009C |
| Reset: | 0x00000111 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[11:4] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY[3:0] | |||||||||
| Access | W | W | W | W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTIRQSEL | SMCPURANGE | TSRANGE | PSWBU | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 1 |
Bits 31:20 – KEY[11:0] Safety key. Must write 0xD5E to enable GPSBR modifications
Bit 3 – EXTIRQSEL
| Value | Description |
|---|---|
| 0 | EXT_IRQ0 |
| 1 | EXT_IRQ1 |
Bit 2 – SMCPURANGE
| Value | Description |
|---|---|
| 0 | Adjusts SM VDDCPU thresholds for 600 MHz max frequency operation. |
| 1 | Adjusts SM VDDCPU thresholds for 800 MHz max frequency operation. |
Bit 1 – TSRANGE
| Value | Description |
|---|---|
| 0 | Sets temperature sensor high threshold to 105°C. |
| 1 | Sets temperature sensor high threshold to 120°C. |