60.7.3 SECUMOD Status Register
The following configuration values are valid for all listed bit names of this register:
0: No alarm generated since the last clear.
1: An alarm has been generated by the corresponding monitor since the last clear.
Note: Even unprotected detectors, such as those without a corresponding bit set in
SECUMOD_NMPR or SECUMOD_BMPR, can set a flag in SECUMOD_SR, but no erase is
performed.
| Name: | SECUMOD_SR |
| Offset: | 0x0008 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DET3 | DET2 | DET1 | DET0 | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VDDCPUH | VDDCOREH | VDDCPUL | VDDCOREL | VBATH | VBATL | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TPMH | TPML | REGANA | JTAG | TST | DBLFM | DWDT_SW | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |