50.6.5 ASRC Valid bit Per Sample Out Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
| Name: | ASRC_VBPS_OUT |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VBPS_OUT3[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VBPS_OUT2[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VBPS_OUT1[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VBPS_OUT0[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 0:3, 8:11, 16:19, 24:27 – VBPS_OUTx Valid Bit Per Sample Out of DSP x
Defines the number of valid bits of the outgoing data of DSP x.
| Value | Name | Description |
|---|---|---|
| 0 | 8_BIT | The 8 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 1 | 16_BIT | The 16 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 2 | 20_BIT | The 20 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 3 | 24_BIT | The 24 LSB of RHR registers are read from the 24-bit DSP output. |
| 4 | 32_BIT | The 24 MSB of RHR registers are the 24-bit output of the DSP. The 8 LSB of the RHR are driven by bits [22:15] of the DSP output. |
| 5 | 10_BIT | The 10 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 6 | 12_BIT | The 12 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 7 | 14_BIT | The 14 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |
| 8 | 18_BIT | The 18 MSB of the 24-bit read from the DSP output are right-aligned on RHR. |