50.6.7 ASRC Trigger Selection Register

This register can only be written if the WPEN bit is cleared in ASRC_WPMR.

Name: ASRC_TRIG
Offset: 0x24
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 TRIGSELOUT3[3:0]TRIGSELOUT2[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 TRIGSELOUT1[3:0]TRIGSELOUT0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 TRIGSELIN3[3:0]TRIGSELIN2[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TRIGSELIN1[3:0]TRIGSELIN0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16:19, 20:23, 24:27, 28:31 – TRIGSELOUTx Output Trigger Source Selection of DSP x

ValueNameDescription
0 GCLKDIV

Internal trigger event, a configurable division of GCLK (see ASRC_RATIOx for divider).

1 I2SMCC0

Trigger event from audio peripheral.

2 I2SMCC1

Trigger event from audio peripheral.

3 PDMC0

Trigger event from audio peripheral.

4 PDMC1

Trigger event from audio peripheral.

5 SSC0 RX

Trigger event from audio peripheral.

6 SSC0 TX

Trigger event from audio peripheral.

7 SSC1 RX

Trigger event from audio peripheral.

8 SSC1 TX

Trigger event from audio peripheral.

9 SPDIFTX

Trigger event from audio peripheral.

10 SPDIFRX

Trigger event from audio peripheral.

Bits 0:3, 4:7, 8:11, 12:15 – TRIGSELINx Input Trigger Source Selection of DSP x

ValueNameDescription
0 GCLKDIV

Internal trigger event, a configurable division of GCLK (see ASRC_RATIOx for divider).

1 I2SMCC0

Trigger event from audio peripheral.

2 I2SMCC1

Trigger event from audio peripheral.

3 PDMC0

Trigger event from audio peripheral.

4 PDMC1

Trigger event from audio peripheral.

5 SSC0 RX

Trigger event from audio peripheral.

6 SSC0 TX

Trigger event from audio peripheral.

7 SSC1 RX

Trigger event from audio peripheral.

8 SSC1 TX

Trigger event from audio peripheral.

9 SPDIFTX

Trigger event from audio peripheral.

10 SPDIFRX

Trigger event from audio peripheral.