50.6.2 ASRC Mode Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
| Name: | ASRC_MR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GT96K | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ASRCEN3 | ASRCEN2 | ASRCEN1 | ASRCEN0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 12 – GT96K Frequency Sampling Greater Than 96 kHz
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Up to 4 DSPs with up to 96 kHz as the upper bound limit of the sampling frequency. |
| 1 | ENABLE |
Up to 2 DSPs with up to 192 kHz as the upper bound limit of the sampling frequency. The number of enabled DSPs is limited to 2. |
Bits 0, 1, 2, 3 – ASRCENx ASRC Stereo Channel x Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | DSPx is disabled. |
| 1 | ENABLE | DSPx is enabled. |