50.6.6 ASRC Channel Configuration Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
| Name: | ASRC_CH_CONF |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHUNK3[2:0] | CHUNK2[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHUNK1[2:0] | CHUNK0[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MONO3 | MONO2 | MONO1 | MONO0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RHROPMODE[2:0] | THROPMODE[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 16:18, 20:22, 24:26, 28:30 – CHUNKx DMA DSP x CHUNK Size
DMA channel chunk size for Receive and Transmit FIFOs of DSP x.
When Receive FIFO of DSP x has CHUNK unread data, the flag ASRC_ISRx.RXCHUNK rises.
When Transmit FIFO of DSP x has CHUNK empty data, the flag ASRC_ISRx.TXCHUNK rises.
| Value | Name | Description |
|---|---|---|
| 0 | 1_DATA | The DMA chunk size must be configured to transfer 1 data for each rising edge of the trigger event. |
| 1 | 2_DATA | The DMA chunk size must be configured to transfer 2 data for each rising edge of the trigger event. |
| 2 | 4_DATA | The DMA chunk size must be configured to transfer 4 data for each rising edge of the trigger event. |
| 3 | 8_DATA | The DMA chunk size must be configured to transfer 8 data for each rising edge of the trigger event. |
| 4 | 16_DATA | The DMA chunk size must be configured to transfer 16 data for each rising edge of the trigger event. |
Bits 8, 9, 10, 11 – MONOx DSP x Mono Operating Mode
| Value | Name | Description |
|---|---|---|
| 0 | DISABLED | DSP operates in Stereo mode. |
| 1 | ENABLED | DSP operates in Mono mode. |
Bits 6:4 – RHROPMODE[2:0] Receive Holding Registers Operating Mode
Optimizes the DMA channels versus the number and type of audio streams to manage
For more details, see DSP and Channel Configuration.
| Value | Name | Description |
|---|---|---|
| 0 | RHRX_UPTO_2CH | The ASRC_RHRx can receive up to 2 audio streams (e.g. 1 stereo channel for each ASRC_RHR). Each ASRC_RHRx is routed on each Stereo DSP x. |
| 1 | RHR0_UPTO_4CH | The ASRC_RHR0 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_RHR0). The ARSC_RHR1 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_RHR1). The ARSC_RHR2 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_RHR2). ASRC_RHR3 must not be used. |
| 2 | RHR01_UPTO_4CH | The ASRC_RHR0 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_RHR0). The ASRC_RHR1 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_RHR1). ASRC_RHR2 and ASRC_RHR3 must not be used. |
| 3 | RHR0_UPTO_6CH | The ASRC_RHR0 can receive up to 6 audio streams (e.g. up to 3 stereo channels on ASRC_RHR0). The ARSC_RHR1 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_RHR1) ASRC_RHR2 and ASRC_RHR3 must not be used. |
| 4 | RHR0_UPTO_8CH | The ASRC_RHR0 can receive up to 8 audio streams (e.g. up to 4 stereo channels on ASRC_RHR0). ASRC_RHR1, ASRC_RHR2 and ASRC_RHR3 must not be used. |
Bits 2:0 – THROPMODE[2:0] Transmit Holding Registers Operating Mode
Optimizes the DMA channels versus the number and type of audio streams to manage.
For more details, see DSP and Channel Configuration.
| Value | Name | Description |
|---|---|---|
| 0 | THRX_UPTO_2CH | The ASRC_THRx can receive up to 2 audio streams (e.g. 1 stereo channel for each ASRC_THR). Each ASRC_THRx is routed on each Stereo DSP x. |
| 1 | THR0_UPTO_4CH | The ASRC_THR0 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_THR0). The ARSC_THR1 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_THR1). The ARSC_THR2 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_THR2). ASRC_THR3 must not be used. |
| 2 | THR01_UPTO_4CH | The ASRC_THR0 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_THR0). The ASRC_THR1 can receive up to 4 audio streams (e.g. up to 2 stereo channels on ASRC_THR1). ASRC_THR2 and ASRC_THR3 must not be used. |
| 3 | THR0_UPTO_6CH | The ASRC_THR0 can receive up to 6 audio streams (e.g. up to 3 stereo channels on ASRC_THR0). The ARSC_THR1 can receive up to 2 audio streams (e.g. 1 stereo channel on ASRC_THR1) ASRC_THR2 and ASRC_THR3 must not be used. |
| 4 | THR0_UPTO_8CH | The ASRC_THR0 can receive up to 8 audio streams (e.g. up to 4 stereo channels on ASRC_THR0). ASRC_THR1,ASRC_THR2 and ASRC_RHR3 must not be used. |