50.6.11 ASRC Interrupt Disable Register of Stereo Channel x
This register can only be written if the WPITEN bit is cleared in ASRC_WPMR.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | ASRC_IDRx |
| Offset: | 0x78 + x*0x04 [x=0..3] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | LOCK | | | | | | | |
| Access | | W | | | | | | | |
| Reset | | – | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | SECE | |
| Access | | | | | | | | W | |
| Reset | | | | | | | | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | TXOVR | TXUDR | TXCHUNK | TXFULL | TXEMPTY | TXRDY | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | – | – | – | – | – | – | |
Bit 30 – LOCK DPLL Locked Interrupt
Disable
Bit 16 – SECE Security/Safety Report Interrupt
Disable
Bit 13 – TXOVR Transmit Over Flow Interrupt Disable
Bit 12 – TXUDR Transmit Under Flow Interrupt Disable
Bit 11 – TXCHUNK Transmit FIFO Chunk Interrupt Disable
Bit 10 – TXFULL Transmit FIFO Full Interrupt Disable
Bit 9 – TXEMPTY Transmit FIFO Empty Interrupt Disable
Bit 8 – TXRDY Transmit Ready Interrupt Disable
Bit 5 – RXOVR Receive Over Flow Interrupt Disable
Bit 4 – RXUDR Receive Under Flow Interrupt Disable
Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Disable
Bit 2 – RXFULL Receive FIFO Full Interrupt Disable
Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Disable
Bit 0 – RXRDY Receive Ready Interrupt Disable
