50.6.4 ASRC Valid bit Per Sample In Register
This register can only be written if the WPEN bit is cleared in ASRC_WPMR.
| Name: | ASRC_VBPS_IN |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VBPS_IN3[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VBPS_IN2[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VBPS_IN1[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VBPS_IN0[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 0:3, 8:11, 16:19, 24:27 – VBPS_INx Valid Bit Per Sample In of DSP x
Defines the number of valid bits of the incoming data of DSP x.
| Value | Name | Description |
|---|---|---|
| 0 | 8_BIT | The 8 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [15:8] of the 24-bit data are driven by the 8 LSB of THR registers to increase the dynamic range of the data sent to DSP. The bits [7:0] are driven by 0s. |
| 1 | 16_BIT | The 16 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [7:0] of the 24-bit data are driven by the bits [15:8] of the THR registers to increase the dynamic range of the data sent to DSP. |
| 2 | 20_BIT | The 20 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [3:0] of the 24-bit data are driven by the bits [19:16] of the THR registers to increase the dynamic range of the data sent to DSP. |
| 3 | 24_BIT | The 24 LSB of THR registers are entered to the DSP. |
| 4 | 32_BIT | The 24 MSB of THR registers are entered to the DSP. |
| 5 | 10_BIT | The 10 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [13:4] of the 24-bit data are driven by the 10 LSB of THR registers to increase the dynamic range of the data sent to DSP. The bits [3:0] are driven by 0s. |
| 6 | 12_BIT | The 12 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [11:0] of the 24-bit data are driven by the bits [11:0] of the THR registers to increase the dynamic range of the data sent to DSP. |
| 7 | 14_BIT | The 14 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [9:0] of the 24-bit data are driven by the bits [13:4] of the THR registers to increase the dynamic range of the data sent to DSP. |
| 8 | 18_BIT | The 18 LSB of THR registers are left aligned on 24-bit data entered to the DSP. The bits [5:0] of the 24-bit data are driven by the bits [17:12] of the THR registers to increase the dynamic range of the data sent to DSP. |