17.5.9.3 Automatic and Software Initiated ZQCS

The UDDRC issues a ZQCS command in the following ways:

• Automatic ZQCS by the UDDRC: in this case, UDDRC sends ZQCS commands to SDRAM periodically. The interval is determined by ZQCTL1.t_zq_short_interval_x1024. This method is used if ZQCTL0.dis_auto_zq is set to 0 (see Register Descriptions).
• ZQCS using direct software request: in this case, the SoC core sends a ZQCS command through software by setting DBGCMD.zq_calib_short to 1. When the ZQCS request is stored in the UDDRC, the register bit is automatically cleared. It is recommended not to set DBGCMD.zq_calib_short signal, in Init, Self-refresh, Deep Power-down operating modes or Maximum Power Saving mode (MPSM). The SoC core can initiate a ZQCS operation only if DBGSTAT.zq_calib_short_busy is low. The DBGSTAT.zq_calib_short_busy signal goes high in the clock after the UDDRC accepts a ZQCS request. It goes low when the ZQCS operation is initiated in the UDDRC. For proper SDRAM operation, user/SoC core should schedule this command frequently. This method is used if ZQCTL0.dis_auto_zq is set to 1.

For self-refresh, command is scheduled after SR/SR-Powerdown is exited. For Deep Power Down or MPSM, command is not scheduled although ZQSTAT.zq_calib_short_busy is de-asserted.