17.5.9.2 LPDDR2/LPDDR3 Devices

The UDDRC supports all the ZQ Calibration commands that are supported by the JEDEC Specification.

  • ZQInit (ZQ Initial Calibration) command performs the initial calibration during the power-up initialization sequence. This command is allowed a time period of tZQinit (determined by INIT5.dev_zqinit_x32).
  • ZQCL (ZQ Long Calibration) command performs long ZQ Calibration after exiting from Self-refresh mode. This command is allowed a timing period of tZQCL (determined by ZQCTL0._t_zq_long_nop). This command is issued automatically when ZQCTL0. dis_srx_zqcl is set to 0. To disable issuing of ZQCL after self-refresh exit, set ZQCTL0. dis_srx_zqcl to 1.
  • ZQCS (ZQ Short Calibration) command is used to perform periodic calibration to account for VT (Voltage/Temperature) variations. A shorter timing window is provided to perform calibration and transfer of values as defined by the timing parameter tZQCS (determined by ZQCTL0._t_zq_short_nop). ZQCS can be performed automatically on a regular interval or through direct software request. For more information, see Automatic and Software Initiated ZQCS.
  • ZQReset (ZQ Calibration Reset) command is used to reset the RON calibration to a default accuracy of ±30% across process, voltage and temperature. This command is used to ensure RON accuracy of ±30% when ZQCS and ZQCL are not used and is allowed a time period of tZQRESET, determined by ZQCTL1.t_zq_reset_nop. The command is issued by using the registers ZQCTL2.zq_reset and ZQSTAT.zq_reset_busy (see Register Descriptions). For more information, see LPDDR2/LPDDR3 ZQ Reset Command.

In LPDDR2/LPDDR3 mode, ZQ Calibration commands are sent out as Mode Register Write commands to the DRAM. The MRW is done to MR10 and the calibration codes for the different commands are as follows:

ZQInit – 0xFF, ZQCL – 0xAB, ZQCS – 0x56 and ZQRest – 0xC3

The UDDRC performs no other activities for the duration of tZQinit, tZQCL, tZQCS, and tZQRESET. The quiet time on the SDRAM channel helps in accurate calibration of SDRAM RON and ODT. All banks are precharged and tRP met before the UDDRC issues the ZQ Calibration commands.