17.5.9.4 LPDDR2/LPDDR3 ZQ Reset Command

In LPDDR2/LPDDR3 mode, the ZQ Reset command is issued by setting ZQCTL2.zq_reset to 1 (see Register Descriptions). When the ZQ Reset operation is complete, the UDDRC automatically clears this register bit. In LPDDR2/LPDDR3 mode, it is recommended not to set this signal in Init, Self-refresh or Deep Power-down operating modes. The SoC core can initiate a ZQ Reset operation only if ZQSTAT.zq_reset_busy is low. This signal goes high in the clock after the UDDRC accepts a ZQ Reset request. It goes low when the ZQ reset command is issued to the SDRAM and the associated NOP period is completed.

For self-refresh, command is scheduled after SR/SR-Powerdown is exited. For Deep Power Down, command is not scheduled although ZQSTAT.zq_reset_busy is de-asserted.