74.7.13.1 Track and Hold Time versus Source Impedance - Sampling Rate

Referring to the figure Equivalent Model of the Acquisition Path, during its tracking phase, the 12-bit ADC charges its sampling capacitor C_S through various serial resistors modeled as R_SOURCE (source output resistor) and R_ON (multiplexer series resistor and the sampling switch series resistor). In case of high output source resistance (for example, a low power resistive divider), the tracking time must be increased to ensure full settling of the sampling capacitor voltage. Note that programming a long tracking time may impact the sampling frequency (f_S). The following formula provides the minimum tracking time that ensures a 12-bit accurate settling.

t_TRACK ≥ 8 x (R_SOURCE + R_ON) x C_S

The ADC Controller (ADCC) counts the tracking time in ADC clock cycles (t_CKADC). This time can be adjusted between 6 and 54 cycles in the fields ADC_MR.TRACKTIM and ADC_EMR.TRACKX. At maximum ADC clock frequency (20 MHz), the maximum tracking time that can be programmed is 2.7 µs. This limits 12-bit accurate sampling to sources having R_SOURCE in the 100 kΩ range. To overcome this limitation, the ADC clock frequency can be decreased.

The following examples show typical use cases of tracking time and sampling frequency calculation.

Example 1: Calculated tracking time is lower than the default (minimum) tracking time.

• Assuming f_CKADC = 8 MHz (t_CKADC = 125 ns), R_SOURCE = 10 kΩ
• The minimum required track time is t_TRACK = 8 x (10 kΩ + 2 kΩ) x 3pF = 288 ns.
• t_TRACK is less than the minimum tracking time (6 x t_CKADC = 750 ns): set TRACKTIM=0 and TRACKX=0.
• The real tracking time is 6 x t_CKADC (750 ns) and the conversion time is:

  t_CONV = t_TRACK + 14 x t_CKADC= 20 x t_CKADC

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• The sampling rate is f_S = 8 MHz / 20 = 400 kS/s.
• The maximum allowable source resistance is R_{SOURCE_MAX} = (6 x t_CKADC) / (3 pF x 8) - 2 kΩ = 29.25 kΩ.

Example 2: Calculated tracking time is greater than the default (minimum) tracking time.

• Assuming f_CKADC = 20 MHz (t_CKADC = 50 ns), R_SOURCE = 20 kΩ
• The minimum required track time is t_TRACK = 8 x (20 kΩ + 2 kΩ) x 3 pF= 528 ns.
• t_TRACK is greater than the minimum tracking time (6 x t_CKADC = 300 ns): set TRACKTIM=5 and TRACKX=1.
• The real tracking time is (4 x (5 + 1) - 10) = 14 x t_{CK_ADC} = 700 ns.
• The conversion time is t_CONV = t_TRACK + 14 x t_CKADC= 28 x t_CKADC.
• The sampling rate is f_S = 20 MHz / 28 = 714.3 kS/s.
• The maximum allowable source resistance is R_{SOURCE_MAX} = (14 x t_CKADC) / (3 pF x 8) - 2 kΩ = 27.2 kΩ.

Example 3: Maximum sampling rate operation.

• Assuming f_CKADC = 20 MHz (t_CKADC = 50 ns), R_SOURCE = 10 kΩ
• The minimum required track time is t_TRACK = 8 x (10 kΩ + 2 kΩ) x 3 pF= 288 ns.
• t_TRACK is less than the minimum tracking time (6 x t_CKADC = 300 ns): set TRACKTIM=0 and TRACKX=0.
• The real tracking time is 6 x t_{CK_ADC} (300 ns) and the conversion time is:

  t_CONV = t_TRACK + 14 x t_CKADC= 20 x t_CKADC

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• The sampling rate is f_S = 20 MHz / 20 = 1 MS/s.
• The maximum allowable source resistance is R_{SOURCE_MAX} = (6 x t_CKADC) / (3 pF x 8) - 2 kΩ = 10.5 kΩ.