19.3.3 SPIx Status Register
- SPITUR is cleared when ON =
0. When IGNTUR =1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | SPIxSTAT |
| Offset: | 0x1808, 0x1828, 0x1848 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXELM[2:0] | |||||||||
| Access | R/HS | R/HS | R/HS | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXELM[2:0] | |||||||||
| Access | R/HSC | R/HSC | R/HSC | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMERR | BUSY | SPITUR | |||||||
| Access | R/C/HS | R/HSC | R/HSC | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMT | SPIROV | SPIRBE | SPITBE | SPITBF | SPIRBF | ||||
| Access | R/HSC | R/C/HS | R/HSC | R/HSC | R/HSC | R/HSC | |||
| Reset | 0 | 0 | 1 | 1 | 0 | 0 |
Bits 26:24 – RXELM[2:0] Receive Buffer Element Count bits (valid in Enhanced Buffer mode)
Bits 18:16 – TXELM[2:0] Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)
Bit 12 – FRMERR SPIx Frame Error Status bit
| Value | Description |
|---|---|
1 | Frame error is detected |
0 | No frame error is detected |
Bit 11 – BUSY SPIx Activity Status bit
| Value | Description |
|---|---|
1 | Module is currently busy with some transactions |
0 | No ongoing transactions (at time of read) |
Bit 8 – SPITUR SPIx Transmit Underrun Status bit(1)
| Value | Description |
|---|---|
1 | Transmit buffer has encountered a Transmit Underrun condition |
0 | Transmit buffer does not have a Transmit Underrun condition |
Bit 7 – SRMT Shift Register Empty Status bit
| Value | Description |
|---|---|
1 | No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit) |
0 | Current or pending transactions |
Bit 6 – SPIROV SPIx Receive Overflow Status bit
| Value | Description |
|---|---|
1 | A new byte/half-word/word has been completely received when the SPIxRXB was full |
0 | No overflow |
Bit 5 – SPIRBE SPIx RX Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB.
Automatically cleared in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[2:0] = 00.
| Value | Description |
|---|---|
1 | RX buffer is empty |
0 | RX buffer is not empty |
Bit 3 – SPITBE SPIx Transmit Buffer Empty Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Automatically cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Enhanced Buffer Mode:
Indicates TXELM[2:0] = 00.
| Value | Description |
|---|---|
1 | SPIxTXB is empty |
0 | SPIxTXB is not empty |
Bit 1 – SPITBF SPIx Transmit Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB.
Automatically cleared in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Enhanced Buffer Mode:
Indicates TXELM[2:0] = 11.
| Value | Description |
|---|---|
1 | SPIxTXB is full |
0 | SPIxTXB not full |
Bit 0 – SPIRBF SPIx Receive Buffer Full Status bit
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[2:0] = 11.
| Value | Description |
|---|---|
1 | SPIxRXB is full |
0 | SPIxRXB is not full |