19.3.7 SPIx Underrun Data Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | SPIxURDT |
| Offset: | 0x1818, 0x1838, 0x1858 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SPIxURDT[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SPIxURDT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPIxURDT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPIxURDT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – SPIxURDT[31:0] SPI Underrun Data bits
These bits are
only used when URDTEN = 1. This register holds the data to
transmit when a Transmit Underrun condition occurs.
| MODE32 | MODE16 | WLENGTH[4:0] | COMMUNICATION | Valid Data Field |
|---|---|---|---|---|
1 | X | 0 | 32-bit | DATA[31:0] |
0 | 1 | 0 | 16-bit | DATA[15:0] |
0 | 0 | 0 | 8-bit | DATA[07:0] |
X | X | 16 < N < 31 | (N+1)-bit | DATA[31:(31-N)] |
X | X | 8 < N < 15 | (N+1)-bit | DATA[15:(15-N)] |
X | X | 1 < N < 7 | (N+1)-bit | DATA[07:(07-N)] |