19.3.2 SPIx Control Register 2

Note:

These bits are effective when AUDEN = 0 only.
Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.

Table 19-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	SPIxCON2
Offset:	0x1804, 0x1824, 0x1844


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
				WLENGTH[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – WLENGTH[4:0] Variable Word Length bits^(1,2)

Value	Description
`11111`	32-bit data
`11110`	31-bit data
`11101`	30-bit data
`11100`	29-bit data
`11011`	28-bit data
`11010`	27-bit data
`11001`	26-bit data
`11000`	25-bit data
`10111`	24-bit data
`10110`	23-bit data
`10101`	22-bit data
`10100`	21-bit data
`10011`	20-bit data
`10010`	19-bit data
`10001`	18-bit data
`10000`	17-bit data
`01111`	16-bit data
`01110`	15-bit data
`01101`	14-bit data
`01100`	13-bit data
`01011`	12-bit data
`01010`	11-bit data
`01001`	10-bit data
`01000`	9-bit data
`00111`	8-bit data
`00110`	7-bit data
`00101`	6-bit data
`00100`	5-bit data
`00011`	4-bit data
`00010`	3-bit data
`00001`	2-bit data
`00000`	See MODE[32,16] bits in SPIxCON1[11:10]

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