12.4.7.5.3 High Frequency Drift Fault Injection

To mimic high frequency drift, the selected reference clock input is purposely divided down by two before entering the time window generator, thus allowing twice as much time for the counter to accumulate its count and double the expected figure.

The count value, once captured, is then compared against the contents of the four threshold limit registers to determine its current deviation against the set criteria. As expected:

  • If BUF[31:0] > HWARN[31:0], HWT interrupt flag is set high with clock warning interrupt output based on the warning threshold limit invoked.
  • If BUF[31:0] > HFAIL[31:0], HFT interrupt flag is also set high with clock failure interrupt output based on fail threshold limit and catastrophic failures invoked.
  • If the counter saturates before the current accumulation time period ends, SATD status bit is set high with clock monitor saturation interrupt output based on the counter having saturated

High frequency drift Fault injection can be activated by setting FLTINJ[1:0] to 2’b10 at random, subject to LOCK/WREN

Note:
  1. FLTINJ[1:0] bits are not self-cleared by hardware. They maintain their programmed value until cleared by software to assist the ISR handler with its discovery process.
  2. Detection of this artificial Fault will not occur if the limit tolerances are set too high. The function is for the detection of 100% margin above nominal or tighter.
Table 12-37. Module Control
FaultClock ConnectionControl
win_clk[*:0]cnt_clk[*:0]ON/WIDTH/FLTINJ[1:0]
Catastrophic Fault Injectionreferencemonitored1/0/11
Low Drift Fault Injectionreferencemonitored1/0/01
High Drift Fault Injectionreferencemonitored1/0/10