19.4.2.5.1 I2S Mode

The Inter-IC Sound (I2S) protocol enables transmission of two channels of digital audio data over a single serial interface. The I2S protocol defines a 3-wire interface that handles the stereo data using the WS/LRCK line. The I2S specification defines a half-duplex interface that supports transmit or receive but not both at the same time. With both SDOx and SDIx available, full-duplex operation is supported by this peripheral, as shown in Figure 19-22.

  • Data Transmit and Clocking:
    • The transmitter shifts the audio sample data’s MSb on the first falling edge of SCKx, after an LRCK transition
    • The receiver samples the MSb on the second rising edge of SCKx
    • The left channel data shifts out while LRCK is low and the right channel data is shifted out while LRCK is high
    • The data in the left and right channels consists of a single frame
  • Required Configuration Settings:

    To set the module to I2S mode, the following bits must be set:

    • AUDMOD[1:0] = 00 (SPIxCON1[25:24])
    • FRMPOL = 0 (SPIxCON1[21])
    • CKP = 1 (SPIxCON1[6])

Setting these bits enables the SDOx and LRCK (SSx) transitions to occur on the falling edge of SCKx (BCLK) and sampling of SDIx to occur on the rising edge of SCKx. Refer to the diagrams shown in Figure 19-22.

Figure 19-22. I2S with 16-Bit Data/Channel or 32-Bit Data/Channel