19.4.2.5.3 Right Justified Mode
In Right Justified mode, the SPI module shifts the audio sample data’s MSb after aligning
the data to the last clock cycle. The bits preceding the audio sample data can be driven
to logic level ‘0’ by setting the DISSDO bit (SPIxCON1[12]) to
‘0’. When DISSDO = 0, the module ignores the
unused bit slot.
- Required Configuration Settings
To set the module to Right Justified mode, the following bits must to be set:
- AUDMOD[1:0] (SPIxCON1[25:24]) =
10 - FRMPOL (SPIxCON1[21]) =
1 - CKP (SPIxCON1[6]) =
0
- AUDMOD[1:0] (SPIxCON1[25:24]) =
This enables the SDOx and LRCK transitions to occur on the rising edge of SCKx, after the LSb is aligned to the last clock cycle. Refer to the sample waveform diagrams shown in Figure 19-25 and Figure 19-26 for 16, 24 and 32-bit audio data transfers.
