19.4.2.5.4 PCM/DSP Mode
The PCM/DSP Protocol mode is available for communication with some codecs and certain DSP (Digital Signal Processor) devices. This mode modifies the behavior of LRCK and audio data spacing. In PCM/DSP mode, the LRCK can be a single bit wide (i.e., 1 SCKx) or as wide as the audio data (16, 24, 32 bits). The audio data is packed in the frame with the left channel data immediately followed by the right channel data. The frame length is still either 32 or 64 clocks when this device is the host.
In PCM/DSP mode, the transmitter drives the audio data’s (left channel) MSb on the first or second transmit edge (see the SPIFE bit (SPIxCON1[1])) of SCKx (after an LRCK transition). Immediately after the (left channel) LSb, the transmitter drives the (right channel) MSb.
- Required Configuration Settings
To set the module to Left Justified mode, the following bits must to be set:
- AUDMOD[1:0] bits
(SPIxCON1[25:24]) =
11
- AUDMOD[1:0] bits
(SPIxCON1[25:24]) =
Refer to the sample waveform diagrams shown in Figure 19-27 and Figure 19-28 for 16, 24 and 32-bit audio data transfers.
