6.2.1 Nonvolatile Memory (NVM) Control Register

Note:
  1. A BOR event Reset will indirectly clear WR by forcing the FSM to terminate the operation underway. The WR bit cannot be set if the operation target address held in the NVMADRx register falls within an unimplemented address space.
  2. Reset occurs only on POR or BOR, but the actual initial state of P2ACTIV that is visible to the user will depend upon which panel is determined to be Active after the Reset exit.
  3. A BMX address error is likely due to a bad NVMSRCADR value. The same error will generate a bus error trap via the interrupt controller. This will aid the software in diagnosing the issue.
  4. WRERR bit will remain set if an attempt is made to execute (WR=1) a reserved PROGOP command. WR bit will not remain set.
  5. “Word” is defined to be a 128-bit data value plus ECC (140 bits total). However, each word program command may consist of a sequence of fractional word programming operations.
  6. Reserved when in Single Boot mode (DUAL_BOOTPRESENT=0).
Table 6-2. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: NVMCON
Offset: 0x3000

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
    WRRE WREC[2:0] 
Access R/HS/HCR/HS/HCR/HS/HCR/HS/HC 
Reset 0000 
Bit 15141312111098 
 WRWRENWRERRNVMPIDLReserved[1:0]   
Access R/S/HCR/WR/C/HSR/WR/HC/HSR/HC/HS 
Reset 000000 
Bit 76543210 
 LOCKDRBV  MVMOP[3:0] 
Access R/WR/C/HSR/WR/WR/WR/W 
Reset 000000 

Bit 20 – WRRE Program/Erase Reset Event bit

ValueDescription
1Warm Reset request during program/erase operation
0No event reported

Write 0 to clear, writing 1 has no effect

Bits 18:16 – WREC[2:0] Program/Erase Error Code bit

ValueDescription
101Row programming operation not completed due to warm Reset
100System bus error during row program operation
011Error reported by Flash panel control logic
010Security access control violation
001Invalid program/erase operation (PROGOP)
000

No error

Unused codes are reserved

Read as ‘000’ if WRERR=0

Bit 15 – WR  Write Control bit(1)

ValueDescription
1Initiates a memory or fuse element program or erase operation
0Program or erase operation is complete and inactive

Bit 14 – WREN Program/Erase Enable bit

ValueDescription
1Allows program/erase cycles
0Inhibits programming/erasing of memory or fuse elements; This bit cannot be updated if either the LOCK bit is set or the WR bit is set

Bit 13 – WRERR Sequence Error Flag bit

ValueDescription
1
Indicates an improper program or erase termination due to:
  • An attempt to execute a reserved PROGOP command
  • An error detected by the Smart Write module, such as Flash failures
  • A BMX address error detected during a row programming operation

This bit cannot be set by software

0

Either a POR or BOR has occurred or software cleared the WRERR bit

Bit 12 – NVMPIDL NVM Power Down in Idle Enable bit

ValueDescription
1

Flash panels enter a Sleep mode (very Low-Power mode) when device enters Idle mode

0Keep Flash and fuse panels powered in Standby mode when device enters Idle mode

Bits 11:10 – Reserved[1:0]

Bit 7 – LOCK Lock bit

ValueDescription
1Program/erase functions are disabled until after the next Reset
0

Program/erase functions are not disabled

Write 1 to set, writing 0 has no effect

Bit 6 – DRBV Data Read Buffer Valid bit

ValueDescription
1Data read buffer holds valid data
0

Data read buffer invalid

Write 0 to clear, writing 1 has no effect

Bits 3:0 – MVMOP[3:0]  NVM Operation Select bits(4,5,6)

ValueDescription
0111-0100Reserved
0011The next WR command will perform a memory page erase operation
0010The next WR command will perform a row program 1 operation
0001The next WR command will perform a word program 1, 3 operation (data source: NVMDATAx)
0000Reserved