13.4.2 Data Size

The DMA Controller can handle 8-bit, 16-bit and 32-bit transactions. Each DMA channel is individually configurable for the data size to be used with the SIZE[1:0] bits (DMAxCH[7:6]). These bits allow the user to specify whether one byte, one 16-bit word or one 32-bit word is transferred per one load or store transaction.

In Byte mode, where SIZE[1:0] is ‘00’, the counter (CNT[31:0]) represents the number of bytes remaining to be transferred. Similarly, the CNT[31:0] bits represent the number of 16-bit words and 32-bit words remaining to be transferred in 16-bit Word (SIZE[1:0] = 01) and 32-bit Word (SIZE[1:0]) modes, respectively.

In Byte mode, byte transfers are accommodated through bit 0 of the address. When bit 0 is ‘0’, the lower byte is addressed, while the upper byte is addressed when bit 0 is ‘1’. For 16-bit word operation, the Address Pointers are 16-bit word-aligned. That is, bit 0 is always ‘0’. For 32-bit word operation, the Address Pointers are 32-bit word-aligned and bits[1:0] are always ‘00’. By default (SIZE[1:0] = 00), the channel is configured for byte-size transactions.