13.4.11 Ping-Pong

With its capability to seamlessly transfer data flow between its internal DMA channels, the 32-bit DMA Controller supports ping-pong operation to assist the CPU in effective and uninterrupted data transfer. By alternating the incoming data flow between two active DMA channels, the CPU can process the available data from one DMA channel while the other active DMA channel is making its own data available to be processed when the CPU has completed its current task.

In DMA controllers with ping-pong mode, channels are paired in fixed combinations such as (0,1), (2,3) and (4,5). Either channel in each pair serves as the initiator channel enabling continuous data transfer. The initiator channel is determined by setting the PCHEN to 1. Each channel alternates between transferring data and preparing for the next transfer, allowing for an uninterrupted data stream with minimal CPU intervention.

The capability relies on proper hardware/software interactions between the CPU and the two DMA channels, 0 and 1; see Figure 13-6. This is configured by setting CHEN (DMAxCH[0]) = 1 and PPEN (DMAxCH[29]) = 1 for both channels. Initially, before the ping-pong operation begins, PCHEN should be set by user software explicitly for the channel that initiates the ping-pong operation.

Each channel of the pair requires its own individual trigger to facilitate transfer. Each channel must be individually set up with its own control settings, source and destination addresses, transfer count and trigger. The channels operate independently in terms of setup, but they are linked in operation through the ping-pong mechanism.

When one DMA channel completes its operation, it triggers the other active channel’s hardware enable input, as shown here. This action sets the other channel’s PCHEN bit (DMAxCH[28]) high. Whenever both PCHEN and CHEN are high (and PPEN = 1), the DMA channel is enabled and ready for data transfer when triggered. This event effectively transfers the data flow from one channel to the other.