13.4.4 Channel Priority and Priority Schemes

While DMA channels can function independently to service different peripherals at the same time, they are still limited by the presence of a single DMA data bus and a single data channel to data space. When two or more channels request the DMA controller to handle a data transfer at the same time, the controller arbitrates the requests and decides which channel receives priority and bus access.

The controller uses two defined arbitration schemes to assign channel priority: Fixed and Round Robin. The PRIORITY bit (DMACON[0]) determines the scheme to be used. In the Round Robin scheme (DMACON[0] = 1), the controller assigns priority and bus grant to the lowest numbered channel for the first time when there is channel contention. Grant determination is evaluated after every iteration of data transfers. For each successive transfer conflict, the next higher channel receives preference, continuing as a cycle through all the channels. If the channel that has priority does not make a request at that time, it is skipped for the next channel in the cycle.

As an example, if Channels 0, 1 and 2 all simultaneously request a data transfer, Channel 0 is serviced; Channels 1 and 2 are then serviced in that order. During the next service request, any request from Channel 1 will receive preference; Channel 2 will receive preference in the following round. Any subsequent transfer requests from Channel 0 will be ignored until all the other channels have received priority once. Typical examples of Round Robin arbitration are shown in Table 13-18.

In contrast, the Fixed scheme (DMACON[0] = 0) always gives priority to the lowest requesting channel number. Using the previous example, if there are several sequential transfer requests involving Channel 0, Channel 0 will always receive preference over other channels. The Fixed priority scheme is the default. Typical examples are shown in Table 13-19.