10.9.1.2 Bus Error Trap During Vector Fetch

It is possible that a bus error could occur while reading a vector location. This could be catastrophic, as the vector value returned will be erroneous. In order to prevent the CPU executing a PFC to an invalid address, the CPU will recognize this scenario, set the Vector Fail flag within the Status Register (SR.VF), and substitute an alternative (register-based) address as the vector address value.

This substitute address is to be held in the Vector Fail Address (VFA) SFR located within the CPU. The user should initialize this address to point to the bus error handler (or a dedicated bus error handler). However, the register is initialized by the CPU to the Reset (first instruction) address during the Reset sequence in order to provide a viable default value should the user neglect to initialize the VFA register.

Note:
  1. No bus error trap request is generated for the interrupt controller, though the CPU will increase its IPL to that of the bus error trap (IPL 14) instead of updating the IPL based on what is received from the interrupt controller.
  2. The interrupt controller will capture the failed exception Interrupt Level register (ILR) and the vector number (VECNUM) in the INTTREG register.
  3. If the default value of the VFA register (i,e, reset vector) is not changed, a bus error that occurs while reading a vector location will raise the CPU IPL to that of the bus error trap (IPL 14) as usual and will vector to the application Reset address.