10.9.1.6 Math Error Traps

The math error trap will execute under the circumstances listed below. The associated math error status and enable bits are located in INTCON4 register.

  1. Divide By Zero: Should an attempt be made to divide by zero, the PC stack will point to the iterated instruction being executed at the time the error is detected. The divide iterations, up to the point that exception processing occurs, will execute as usual (though with meaningless results).
  2. DSP Overflow: If the following conditions are all true, an Overflow of AccA (OVA) math error trap will be taken.
    1. OVATE bit is set (INTCON4[21])
    2. Accumulator A is operating with 1.63 saturation disabled or in 9.63 mode
    3. An arithmetic operation caused an overflow from bit 63 of accumulator A
  3. DSP Overflow: If the following conditions are all true, an Overflow of AccB (OVB) math error trap will be taken.
    1. OVBTE bit is set (INTCON4[20])
    2. Accumulator B is operating with 1.63 saturation disabled or in 9.63 mode
    3. An arithmetic operation caused an overflow from bit 63 of accumulator B
  4. DSP Overflow: If the following conditions are all true, an accumulator Catastrophic Overflow (COV) math error trap will be taken.
    1. COVTE bit is set (INTCON4[19])
    2. Either Accumulator A or B is operating with all saturation disabled
    3. An arithmetic operation caused an overflow from bit 71 (Catastrophic Overflow) of the accumulator with all saturation disabled
  5. DSP Shift Out of Range: If an attempt is made to execute SFTAC with a shift value of greater than 32 or less than -32, the instruction will complete (without a result write) and a math trap will be generated.