10.9.1.3 Illegal Opcode Error
An illegal opcode error trap is asserted when an attempt is made to execute an illegal opcode; it is conditional upon the commitment of a speculatively executed instruction (so it cannot be asserted until the R-stage). An illegal opcode trap is asserted for:
- an attempt to execute any opcode slot within the opcode map that is not allocated an instruction. In addition to unused opcode slots, this also includes any unused sub-opcode slots.
- an attempt to PFC to the second word of a two-word instruction, using the instruction word identifier bit.
- an attempt to execute any unimplemented coprocessor instruction, including any opcode that includes coprocessor select opcode bits (‘zz’ bits) for an unimplemented coprocessor.
- an attempt to PFC to an odd 16-bit instruction address within what is defined as a 32-bit instruction word (Most Significant opcode bit set).